1. Field of Use
This invention pertains to data processing systems and more particularly to distributed bus priority systems.
2. Prior Art
In prior art systems, the subsystem units which connect to a distributed bus priority system, each include bus logic request circuits which control access to a system bus on a priority basis as a function of the unit's positional priority relative to one en of the system bus. Certain input/output subsystem units have been given higher positional priority than other types of input/output subsystem units. However, these I/O units are connected to make low priority requests while the other types of I/O units are connected to make high priority requests. Since the higher priority positioned I/O units are allowed to request as many bus cycles as needed, it was deemed necessary to include logic circuits within the higher priority positioned I/O units for enabling the preemption of bus cycles for carrying out higher priority requests.
However, in such prior art systems, the central subsystem (CSS) units include logic circuits which enable them to be the lowest priority and are able to gain access to the system bus on a cycle stealing basis when it is idle. This type of system is disclosed in U.S. Pat. No. 4,724,519.
The arrangement enables the CSS units to access the system bus in a round robin fashion for processing simultaneous CSS requests That is, each CSS unit is in turn granted a single system bus cycle until all simultaneous CSS requesters have been granted bus access.
The major disadvantages of the above arrangement is that a high priority request could be delayed for several cycles. This could impair overall system performance, in addition to increasing the possibility of system bus saturation. Moreover, when the need arises to expand the number of CSS units which have separate interfaces to the system bus, this adds further cycle delays and increases the likelihood of bus saturation.
Accordingly, it is a primary object of the present invention to provide an improved bus access system.
It is a further object of the present invention to provide an improved bus access system for use by several CSS units which operates in a manner to reduce the likeness of bus saturation.